Present day state-of-the-art design technique, logic synthesis, is really only a mapping between different levels of physical abstraction.
One of the most difficult problems in design automation is the inability to get timing closure at even the gate level effectively. This forces designers to do two designs: logic design and timing design. Otherwise, the designer simply over-designs the circuits, because the best case timing is much different from the worst case timing. In other cases, designers insist on control of device layout so that they can evaluate all of the tradeoffs between implementation and timing.
Present computer aided design (CAD) systems for the design of electronic circuits, referred to as ECAD or Electronic CAD systems, assist in the design of electronic circuits by providing a user with a set of software tools running on a digital computer with a graphical display device. Typically, five major software program functions run on the ECAD system: a schematic editor, a logic compiler, a logic simulator, a logic verifier, and a layout program. The schematic editor program allows the user of the system to enter and/or modify a schematic diagram using the display screen, generating a net list (summary of connections between components) in the process. The logic compiler takes the net list as an input, and using a component database puts all of the information necessary for layout, verification and simulation into a schematic object file or files whose format(s) is(are) optimized specifically for those functions. The logic verifier checks the schematic for design errors, such as multiple outputs connected together, overloaded signal paths, etc., and generates error indications if any such design problems exist. The logic simulator takes the schematic object file(s) and simulation models, and generates a set of simulation results, acting on instructions initial conditions and input signal values provided to it either in the form of a file or user input. The layout program generates data from which a semiconductor chip (or a circuit board) may be laid out and produced.
The Modular Design Environment (MDE) produced by LSI Logic Corporation of Milpitas, Calif., is a suite of software tools for computers running the UNIX operating system. MDE comprises a schematic editor (LSED) and a simulator (LDS), among other software programs, and provides an example of commercially available tools of the aforementioned type. Another example of a schematic editor, schematic compiler, and schematic simulator may be found in the SCALDstation produced by Valid Logic Systems, Inc. of Mountain View, Calif.
VHDL, or VHSIC (Very High Speed Integrated Circuit) Hardware Description Language, is a recently developed, higher level language for describing complex devices. The form of a VHDL description is described by means of a context-free syntax together with context-dependent syntactic and semantic requirements expressed by narrative rules. VHDL is described in IEEE Standard VHDL Language Reference Manual (IEEE Std 1076-1987), and is also known as MIL-STD-454, Regulation 64.
VHDL represents an important step forward in design specification languages because the semantics, or intent, of the language constructs are clearly specified. In theory, VHDL unambiguously describes a designer's intended system or circuit behavior, in syntactic terms. The "design entity" is the primary hardware abstraction in VHDL. It represents a portion of a hardware design that has well-defined inputs and outputs and performs a well-defined function. A design entity may represent an entire system, a sub-system, a board, a chip, a macro-cell, a logic gate, or any level of abstraction in between. A "configuration" can be used to describe how design entities are put together to form a complete design.
VHDL supports three distinct styles for the description of hardware architectures. The first of these is "structural" description, wherein the architecture is expressed as a hierarchical arrangement of interconnected components. The second style is "data-flow" description, in which the architecture is broken down into a set of concurrent register assignments, each of which may be under the control of gating signals. This description subsumes the style of description embodied in register transfer level (RTL) descriptions. The third style is "behavioral" description, wherein the design is described in sequential program statements similar to a high-level programming language. In the main hereinafter, the behavioral description style is discussed. However, all three styles may be intermixed in a single architecture.
A methodology for deriving a lower-level, physically-implementable description, such as a RTL description of the higher level (e.g. VHDL) description, via an intermediate rule-based tool such as Prolog, is disclosed herein.
Prolog is a programming language based on predicate logic. It can be used for "intelligent" tasks like mathematical theorem proving. A Prolog program is a set of rules which define the relationships among objects. The general form of a Prolog rule is a "horn" clause, in which a specified "goal" is true if certain conditions are true. Execution of a Prolog program involves finding a proof for the goal in question, using unification and resolution. An important aspect of Prolog employed in the present invention is "term.sub.-- expansion", which converts predefined rules into ordinary Prolog clauses.
The schematic editor of the ECAD system is usually an interactive software tool which enables the user to select from a number of circuit elements which will be graphically displayed upon a graphical/text display device, hereinafter referred to as the display screen, connected to the computer. These displayed elements may then be interconnected by lines representing wires drawn on the display screen by the user through interaction with the computer via a position input device, which may be a pointing device such as a mouse, trackball, joystick, graphic tablet, or keyboard used to enter coordinates on the display screen and commands to the software tool. The circuit elements and their interconnecting wires form a schematic diagram which is viewed either in whole or in part on the display screen. As the schematic diagram is constructed on the display screen, the computer represents these elements in a storage medium, which may be a memory or a mass storage device such a magnetic disk drive. These representations, taken as a group, form a numerical representation of the schematic which has been entered by the user in a standardized form which is understood by the schematic editor. Typically, this form has been optimized for the entry and modification of schematic information.
Often, schematic editors allow for hierarchical design whereby a previously created and stored circuit may be recalled and viewed and used as a macro-level component in other circuits. Multiple instances of such macro-level components may be included in a higher-level schematic diagram. The schematic editor creates data structures effectively replicating the macro-level component. The higher-level schematic may further be incorporated as a macro-level component into yet higher-level schematic diagrams, and so on.
Typically, the form of user interaction with the schematic editor is an object-oriented screen display whereby the user thereof may manipulate objects on the screen through the use of a pointing device. A pointing device is any device through the use of which a user may "point" to and identify objects on a display screen. Such object-oriented interfaces are well known to those skilled in the art. One example of such and interface is the Macintosh Finder for the Apple Macintosh computer, both produced by Apple Computer, Inc. Another example of such an interface is that of Microsoft Windows, produced by Microsoft Corp. of Redmond, Wash.
In order to simulate the performance of the circuit, it is necessary to run a simulator. A simulator is a software tool which operates on: a digital representation, or simulation model of a circuit, a list of input stimuli representing real inputs, and data about the performance characteristics of the represented circuit elements; and generates a numerical representation of the response of the circuit which may then either be viewed on the display screen as a list of values or further interpreted, often by a separate software program, and presented on the display screen in graphical form. Typically, the graphical presentation is designed to produce an image similar to what one would see on an oscilloscope or logic analyzer screen monitoring a real circuit connected as described in the schematic diagram if the real inputs represented by the list of input stimuli were applied. The simulator may be run either on the same computer which is used for schematic entry, or on another piece of electronic apparatus specially designed for simulation. Simulators which run entirely in software on a general purpose computer, whether the same as or different from the one used for schematic entry, will hereinafter be referred to as software simulators. Simulations which are run with the assistance of specially designed electronic apparatus will hereinafter be referred to as hardware simulators. An example of a such a hardware simulator is described in U.S. Pat. No. 4,587,625, entitled PROCESS FOR SIMULATING DIGITAL STRUCTURES. Usually, software simulators perform a very large number of calculations compared to the number required for schematic entry and operate slowly from the user's point of view. In order to optimize performance, the format of the simulation model is designed for very efficient use by the simulator. Hardware simulators, by nature, require that the simulation model comprising the circuit description and its performance parameters be communicated in a specially designed format. In either case, a translation process is required.
Simulation is often provided by utilizing simulation models at one or more of several different levels. Component-level models attempt to describe the exact behavior of a specific component, such as a gate or transistor, when it is acted upon by a stimulus or stimuli. Behavioral-level models provide a simplified model of extremely complicated devices, such as a microprocessor, or an operational amplifier. Such models, if simulated exactly on a transistor by transistor basis, would become prohibitive in terms of the size of their descriptions and the number of calculations and amount of computing time required to completely simulate their function. In response to this, the behavioral-level model provides a logical or mathematical equation or set of equations describing the behavior of the component, viewed as a "black box". Such models may either provide a very complete and accurate description of the performance of the modeled device, or a simple description of the types of signals one might expect the modeled device to produce. For example, a behavioral model of a microprocessor might provide the user with the capability of issuing various types of bus cycles, but not the capacity to actually simulate the execution of a program. Circuit-level models typically comprise a plurality of component-level and/or behavioral-level models and the descriptions of their interconnections for the purpose of simulating the performance of a complete circuit comprising a number of interconnected components. Simulations of hierarchical designs require that the included macro-level components also be simulated. Circuit-level or behavioral-level models of the macro-level components may be used to simplify this task.
The simulation model used by the simulator is usually derived from the output of the schematic editor by a schematic compiler, also making use of information about performance characteristics of the circuits, often stored in simulation libraries. Simulation libraries contain simulation characteristics of numerous circuit components and are typically maintained in files on the computer's on-line storage devices. The schematic compiler is a software tool which interprets the circuit element and interconnection information generated by the schematic editor and the performance characteristics stored in the simulation libraries, and reorganizes and translates them into the simulation model for the circuit. Occasionally, either the simulator or the schematic editor includes the function of a schematic compiler, in which case, separate compilation is not required.
Simulators often allow several different types of simulation. One type is a complete simulation run, where an initial set of conditions is specified, a set of input stimuli is defined and the duration of the simulated run is specified. The simulator then operates on the data and produces a file of the results which may be displayed. Another type of simulation, similar to the complete simulation run is an event-terminated run, whereby the simulation is run until a certain pre-specified event occurs in the simulation results. The simulation may be terminated immediately at that point, or run for some simulated duration afterwards. One final type of simulation run is a stepped simulation run, whereby the current simulation may be "stepped" by one unit of time, or one clock cycle, or some other similar criterion.
The process of designing an electronic circuit on a typical ECAD system is done in several discrete steps. A schematic diagram of the circuit is entered interactively through the use of a schematic editor which produces a digital representation of the circuit elements and their interconnections. The user of the ECAD system then prepares a list of input stimuli representing real input values to be applied to the simulation model of the circuit. This representation is then compiled by a schematic compiler and translated into a form which is best suited to simulation. This new, translated representation of the circuit is then operated upon by a simulator, which produces numerical output analogous to the response of a real circuit with the same inputs applied. This output is then usually presented to the user in a graphical fashion. By viewing the simulation results, the user may then determine if the represented circuit will perform correctly when it is constructed. If not, he may then re-edit the schematic of the circuit using the schematic editor, re-compile and re-simulate. This process is performed iteratively until the user is satisfied that the design of the circuit is correct.
While the design process outlined herein is significantly faster and less error prone than manual design, the user must still go through the design process in a number of discrete, disjointed steps. The design process is broken into two or three separate thought processes. First, the user must enter the schematic into the computer using a schematic editor. Second, the user completes the schematic entry process and instructs the appropriate software tool (schematic editor, schematic compiler, or simulator) to prepare the design for simulation. Third, the user must create simulation stimuli, usually with the assistance of yet another software tool, and instruct the simulator to apply these stimuli to the simulation model of the circuit being designed. The results are viewed by the user, who then makes a judgement about whether the design is performing correctly.
In modern digital systems, designs incorporating 20,000 logic gates or more are not uncommon. Also, in modern analog electronic systems, especially where the function being designed is intended to be incorporated into an integrated circuit, it is not uncommon to encounter designs comprising many hundreds of transistors and other electronic devices. These designs, due to their complexity, present a need for frequent simulation of the circuit being designed in small parts before it is simulated as a whole. This is necessary because errors in a small portion of the circuit are easy to detect when that small portion is simulated in isolation. On the other hand, when the entire circuit is simulated, compound errors may occur which mask other errors. Further the enormity of modern circuit complexity makes the errors in the small portion of the circuit difficult to recognize.
This need for frequent, partial simulation is somewhat frustrated by current ECAD systems which require the user to break his train of thought in the design process and to move from one tool to the next. Some ECAD systems have begun to attack this problem by providing "windowed" displays, whereby the user may display the output of several software programs at once on different portions of the display screen. This design environment, however is still not fully interactive. In order to simulate small portions of a circuit, the user may need to design special test circuits incorporating those small portions of the circuit and simulate them in isolation.
As described, for example, in parent case (U.S. patent application Ser. No. 08/077,294) a top-down design process for electronic systems and devices may proceed in an organized, hierarchical manner, from a highest level description of an electronic design, through various stages of refinement, to a lowest level description of the design. These levels may include system level, architectural level, behavioral level, register-transfer (RT) level, logic level and structural level. As the design is being refined, the engineer must make choices and explore alternatives to ensure that a valid, implementable design can and will be achieved. Changes made at one level of abstraction will typically influence the design at other stages of abstraction. Hence, it is important that the designer have ready access to various bits and pieces of information about the circuit or system under design at various stages of abstraction. The present invention describes techniques for organizing and providing such information with a high degree of concurrency, and a facile user-interface for accessing and manipulating such information.